Semiconductor components are used in the fabrication of electronic items, such as multi chip modules. For example, bare semiconductor dice can be mounted to substrates such as printed circuit boards, and ceramic interposers. Flip chip mounting of bumped dice is one method for electrically connecting the dice to the substrates. With flip chip mounting, solder bumps on the device bond pads are reflowed into electrical contact with contacts on the substrate. Chip on board (COB) mounting of dice to substrates can also be employed. With chip on board mounting, wire bonds are formed between the device bond pads and contacts on the substrate.
Chip scale packages are sometimes used in place of bare dice for fabricating electronic items. Typically, a chip scale package includes a substrate bonded to the face of a bare die. The substrate includes the external contacts for making outside electrical connections to the chip scale package. The external contacts for one type of chip scale package include solder balls arranged in a dense array, such as a ball grid array (BGA), or a fine ball grid array (FBGA). In general, chip scale packages can be mounted to substrates using the same mounting methods employed with bare dice (e.g., flip chip, COB).
Besides making permanent electrical connections between semiconductor components and substrates for fabricating multi chip modules or other packaging applications, electrical connections are sometimes necessary for testing applications. For example, bare dice are tested in the manufacture of known good die (KGD). Chip scale packages must also be tested prior to use in electronic items. In these cases the electrical connections with the device bond pads for bare dice, or with the external contacts for chip scale packages, are preferably non-bonded, temporary electrical connections.
In either packaging or testing applications, the substrate includes contacts that must be physically aligned with, and then electrically connected to corresponding contacts on the component. As semiconductor components become smaller, and the contacts become denser, aligning and electrically connecting the components to substrates become more difficult. Accordingly, a key design consideration in the packaging and testing of semiconductor components, is the method for aligning and connecting the components to the mating substrates.
An example of a test assembly for semiconductor components is shown in FIG. 1. The test assembly includes a carrier 2 adapted to temporarily package a semiconductor component 9 for testing. The component 9 includes contacts 11 in electrical communication with integrated circuits on the component 9. Mounted within the carrier 2 is an interconnect 4. The interconnect can be attached to the carrier 2 using an adhesive layer 6. Included on the interconnect 4 are patterns of contacts 8 configured to make separate electrical connections with the contacts 11 on the component 9. Exemplary carriers and interconnects are more fully described in U.S. Pat. Nos. 5,519,332 and 5,541,525 to Wood et al.
In the test assembly of FIG. 1, the interconnect 4 is the substrate to which the component 9 must be aligned and connected. An assembly device can be used for aligning and connecting the component 9 to the interconnect 4. This type of assembly device is described in the above cited patents, and also in U.S. Pat. No. 5,634,267 to Wood et al. In general the assembly device aligns the component and the interconnect, and then brings the component and interconnect together to place the contacts on the component in electrical communication with the contacts on the interconnect.
To facilitate the aligning and connecting process, the tips of the contacts 8 on the interconnect 4 are preferably in the same plane, and the surfaces of the contacts 11 on the component 9 are preferably in the same plane. However, this may not always be the case. Also, the contacts 8 on the interconnect 4 are preferably parallel to either the top or the bottom surfaces of the carrier 2, because these surfaces can be used to mount the carrier 2 to the assembly device. However, in actual practice, the plane containing the contacts 8 is rarely parallel to either the top or the bottom surface of carrier 2. This makes the alignment and connecting process more difficult because these differences in planarity can cause misalignment between the contacts 8 on the interconnect 4 and the contacts 11 on the component 9.
Referring to FIG. 2, another interconnect 4A is shown attached to another carrier 2A using an adhesive layer 6A. Contacts 8A on the interconnect 4A are designed to be electrically connected to the contacts 11 on the component 9 which is being held by a vacuum quill 7 of the assembly device. Plane A is the plane containing the bottom surface of the carrier 2A. Plane B is the plane containing the bottom surface of interconnect 4A. Plane C is the plane containing the top surface of the interconnect 4A. Plane D is the plane containing the contacts 8A. Plane E is the plane containing the surface of component 9 and the contacts 11.
Due to the fabrication process that is used to manufacture interconnects, planes B, C and D can be made substantially planar. However, due to variations in the thickness of the adhesive layer 6A, planes B, C and D are rarely parallel to plane A. Accordingly, even if plane E can be properly oriented with respect to plane A, plane E is not necessarily parallel to or appropriately aligned with plane D or contacts 8A.
One aspect of prior art assembly devices is that most devices are typically able to align the component and interconnect in only four degrees of freedom (X, Y, Z, .THETA.). Alignment of the component and interconnect in the other two degrees of freedom (.PHI., .PSI.) is usually not performed. Accordingly, when the component and interconnect are moved together in the Z-axis direction, the contacts on the component may not always engage the contacts on the interconnect along the same plane. This misalignment can cause pivoting of the component, or interconnect, and further misalignment. Also, the potential of misalignment can require overdriving the component, or the interconnect, in the Z-axis direction to make reliable electrically connections. This overdrive can damage the contacts on the components and substrate.
The same alignment problems as outlined above may also be present in flip chip mounting of components to circuit boards. In this case assembly devices such as aligner bonder tools can be used to align and then bond semiconductor dice to a substrate. A representative aligner bonder tool is disclosed in U.S. Pat. No. 4,899,921 to Bendat et al. These types of tools typically require two separate platforms whose movement must be coordinated. In addition, split vision optics with movable optical probes can be required to view aligned portions of the dice and substrate. The different types of mechanisms required for alignment and optics makes aligner bonder tools relatively complicated and difficult to operate with high precision.
Another example of a semiconductor process involving alignment occurs during wafer probe testing. During probe testing a probe card must be aligned and placed in electrical contact with the wafer. With one type of probe card, needle probes make the electrical connections with contacts on the wafer. Routine maintenance of these probe cards includes checking the position of the needle probes in relation to the contacts on the wafer. However, even with periodic maintenance, the tips of the needle probes can be misaligned in the X, Y and Z-directions. Consequently, some of the needle probes may be misaligned with the contacts on the wafer. The same situation can occur due to differences in the X, Y and Z-direction locations of the contacts on the wafer. If the needle probes cannot flex enough to compensate for misalignment, then the resultant electrical connections can be poor.
Besides the above examples, alignment problems can occur in other semiconductor packaging or assembly processes such as wire bonding and adhesive bonding of dice to leadframes. Another manufacturing process involving alignment occurs during fabrication of flat panel field emission displays (FEDs). An individual field emission display pixel includes emitter sites formed on a baseplate. Electrons emitted by the emitter sites strike phosphors contained on a display screen to form an image. During fabrication of the field emission display it is necessary to align the baseplate with the display screen. However, field emission displays are typically constructed as a sealed package with a vacuum space between the baseplate and the display screen. This spaces complicates the alignment procedure because most alignment devices, such as aligner bonder tools, are constructed to bring the mating components into physical contact.
Due to the foregoing, it would be desirable for an assembly device for semiconductor components to be capable of alignment in six degrees of freedom including three translational degrees of freedom (X, Y, Z) and three rotational degrees of freedom (.THETA., .PHI., .PSI.). The present invention is directed to an automated assembly device capable of alignment in six degrees of freedom. The assembly device can align semiconductor components, or substrates, in three translational and three rotational degrees of freedom, while maintaining a high degree of accuracy and speed.